回复第 2 楼 Jerry Fan于2010-03-07 06:18:25发表:
叙述得有点简单，不好判断是什么问题。
我的开发流程是：
tar -zxvf petalinux-v0.40-final.tar.gz
source settings.sh
新建一个platform xupv5-dma：
petalinux-new-platform -v Xilinx -p xupv5-dma -k 2.6
make menuconfig
在 Vendor Product Selection 中选择Vendor = Xilinx, Products =
xupv5-dma，依次选择exit推出，点yes。
在EDK新建工程xupv5-dma，选择开发板xupv5-lx110t，配置硬件：串口，Flash，DDRram，1 timer等。
system.mhs文件开头是：
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03
Build EDK_K_SP3.6
# Sat Mar 06 20:05:04 2010
# Target Board: Xilinx XUPV5-LX110T Evaluation Platform Rev A
# Family: virtex5
# Device: xc5vlx110t
# Package: ff1136
# Speed Grade: -1
# Processor: microblaze_0
# System clock frequency: 125.00 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 288 MB
# - FLASH = 32 MB
# - DDR2_SDRAM = 256 MB
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT =
fpga_0_Hard_Ethernet_MAC_PHY_MII_INT, DIR = I, SENSITIVITY =
LEVEL_LOW, SIGIS = INTERRUPT
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR =
IO, VEC = [0:7]
PORT fpga_0_LEDs_Positions_GPIO_IO_pin =
fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin =
fpga_0_Push_Buttons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin =
fpga_0_DIP_Switches_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC =
[7:30]
PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC =
[0:15]
PORT fpga_0_FLASH_Mem_ADV_LDN_pin = fpga_0_FLASH_Mem_ADV_LDN, DIR =
O
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT,
DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr,
DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin =
fpga_0_DDR2_SDRAM_DDR2_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin =
fpga_0_DDR2_SDRAM_DDR2_CAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE, DIR
= O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n,
DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin =
fpga_0_DDR2_SDRAM_DDR2_RAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n,
DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk,
DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin =
fpga_0_DDR2_SDRAM_DDR2_Clk_n, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM, DIR
= O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS, DIR =
IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n,
DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ, DIR =
IO, VEC = [63:0]
PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin =
fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_TXD_0, DIR = O, VEC = [7:0]
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin =
fpga_0_Hard_Ethernet_MAC_GMII_RXD_0, DIR = I, VEC = [7:0]
PORT fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin =
fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0, DIR = I
PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin =
fpga_0_Hard_Ethernet_MAC_MDC_0, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin =
fpga_0_Hard_Ethernet_MAC_MDIO_0, DIR = IO
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS =
RST
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
PARAMETER C_FAMILY = virtex5
PARAMETER C_INSTANCE = microblaze_0
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
PORT MB_RESET = mb_reset
PORT Interrupt = Interrupt
END
双击MicroBlaze_0选择divider和bufferier。
在Port选项，debug-module，interruption选择new
connection，在xps_intc_0中加入debug_interrupt_module，参考赵峰《FPGA上的嵌入式系统设计实例》。
在EDK的software中点击software platform
settings，OS选择PetaLinux，drivers中选择相应memory。确定。
Software选项点击generate library and BSPs。
把工程文件 xupv5-dma 复制到
$PETALINUX/hardware/user-platforms/目录下，在该目录中输入命令：
petalinux-copy-autoconfig -v Xilinx -p xupv5-dma -k 2.6
在$PETALINUX/software/petalinux-dist目录下输入：
make menuconfig
Select Customize Kernel Settings and Customize Vendor/User Settings
选择exit-> yes
Customize Kernel Settings -> Device Drivers -> Network device
support -> Ethernet (1000Mbit) -> Select Xilinx 1000Mbit
EMACLITE support
Customize Kernel Settings -> Device Drivers -> Character
Device support -> Serial devices ->select Xilinx UARTLITE and
console on Xilinx UARTLITE
Customize Vendor/User Settings -> System Settings -> Network
Address
Customize Vendor/User Settings -> System Settings -> Flash
Partition Table -> Partition 3 Size = 80000
Exit, 退出
make clean 清除上回编译镜像文件
make dep 建立文件关联
make all 编译
之后在/tftpboot目录下生成所有镜像文件，复制到工程目录下。
用EDK下载download.bit
打开XMD，连接Microblaze
dow –data tftpboot/image.bin 0x90000000 （DDR RAM 起始地址）
con 0x90000000
在此期间超级终端输出如下：
-- Entering main() --
Starting MemoryTest for DDR2_SDRAM:
Running 32-bit test...PASSED!
Running 16-bit test...PASSED!
Running 8-bit test...PASSED!
-- Exiting main() --
Found romfs @ 0x901ac08c (0x000ee000)
#### klimit 901c4000 ####
Moving 0x000ee000 bytes from 0x901ac08c to 0x901c3c8c
New klimit: 0x902b2000
L
到L就停下来了，正常启动应该是：
Found romfs @ 0x24207000 (0x00231000)
#### klimit 2421e000 ####
Moving 0x00231000 bytes from 0x24207000 to 0x2421d9c8
New klimit: 0x2444f000
Linux version 2.6.20-uc0 (bennyc@bennyc) (gcc version 3.4.1 (
PetaLinux 0.20 Bui
ld -rc1 050607 )) #1 Tue Nov 6 11:08:10 EST 2007
setup_cpuinfo: initialising
。。。
PetaLogix网站上对image.bin的说明是：
image.bin The Linux kernel and root filesystem image in binary
format
我想可能是root filesystem image启动了，但Linux kernel没有正常启动，不知是不是？
